Vijaykrishnan Narayanan

A. Robert Noll Chair Professor of Computer Science and Engineering and Electrical Engineering

Vijaykrishnan Narayanan

Huck Affiliations

Publication Tags

Data Storage Equipment Tunnels Field Effect Transistors Machine Learning Heterojunctions Networks (Circuits) Neural Networks Particle Accelerators Sorting Static Random Access Storage Macros Random Access Storage Torque Energy Harvesting Costs Performance Application Specific Integrated Circuits Energy Conservation Demonstrations Tunnel Field Effect Transistors Electric Potential Routers Communication Energy Feedback

Most Recent Papers

Monolithic 3D+-IC based massively parallel compute-in-memory macro for accelerating database and machine learning primitives

Akshay Krishna Ramanathan, Srivatsa Srinivasa Rangachar, Je Min Hung, Chun Ying Lee, Cheng Xin Xue, Sheng Po Huang, Fu Kuo Hsueh, Chang Hong Shen, Jia Min Shieh, Wen Kuan Yeh, Mon Shu Ho, Hariram Thirucherai Govindarajan, Jack Sampson, Meng Fan Chang, Vijaykrishnan Narayanan, 2020, on p. 28.5.1-28.5.4

One-Shot Refresh

Hongtao Zhong, Mingyang Gu, Yu Wang, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs on p. 3402-3406

FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks

Nagadastagiri Challapalle, Sahithi Rampalli, Nicholas Jao, Akshaykrishna Ramanathan, John Sampson, Vijaykrishnan Narayanan, 2020, Journal of Signal Processing Systems on p. 1247-1261

Communication-efficient k-means for Edge-based machine learning

Hanlin Lu, Ting He, Shiqiang Wang, Changchang Liu, Mehrdad Mahdavi, Vijaykrishnan Narayanan, Kevin S. Chan, Stephen Pasteris, 2020, on p. 595-605

Optimization of Intercache Traffic Entanglement in Tagless Caches with Tiling Opportunities

S. R. Swamy Saranam Chongala, Sumitha George, Hariram Thirucherai Govindarajan, Jagadish Kotra, Madhu Mutyam, John Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems on p. 3881-3892

AIGuide

Nelson Daniel Troncoso Aldas, Sooyeon Lee, Chonghan Lee, Mary Beth Rosson, John M. Carroll, Vijaykrishnan Narayanan, 2020,

Look-up table based energy efficient processing in cache support for neural network acceleration

Akshay Krishna Ramanathan, Gurpreet S. Kalsi, Srivatsa Srinivasa, Tarun Makesh Chandran, Kamlesh R. Pillai, Om J. Omer, Vijaykrishnan Narayanan, Sreenivas Subramoney, 2020, on p. 88-101

Robust Coreset Construction for Distributed Machine Learning

Hanlin Lu, Ming Ju Li, Ting He, Shiqiang Wang, Vijaykrishnan Narayanan, Kevin S. Chan, 2020, IEEE Journal on Selected Areas in Communications on p. 2400-2417

IMC-SORT

Zheyu Li, Nagadastagiri Challapalle, Akshay Krishna Ramanathan, Vijaykrishnan Narayanan, 2020, on p. 45-50

Design insights of non-volatile processors and accelerators in energy harvesting systems

Keni Qiu, Mengying Zhao, Zhenge Jia, Jingtong Hu, Chun Jason Xue, Kaisheng Ma, Xueqing Li, Yongpan Liu, Vijaykrishnan Narayanan, 2020, on p. 369-374

Most-Cited Papers

Cache revive

Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das, 2012, on p. 243-252

Architecture exploration for ambient energy harvesting nonvolatile processors

Kaisheng Ma, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yongpan Liu, Jack Sampson, Yuan Xie, Vijaykrishnan Narayanan, 2015, on p. 526-537

Synchronized charge oscillations in correlated electron systems

Nikhil Shukla, Abhinav Parihar, Eugene Freeman, Hanjong Paik, Greg Stone, Vijaykrishnan Narayanan, Haidan Wen, Zhonghou Cai, Venkatraman Gopalan, Roman Engel-Herbert, Darrell G. Schlom, Arijit Raychowdhury, Suman Datta, 2014, Scientific Reports

Tunnel FET technology

Suman Datta, Huichu Liu, Vijaykrishnan Narayanan, 2014, Microelectronics and Reliability on p. 861-874

A case for heterogeneous on-chip interconnects for CMPs

Asit K. Mishra, N. Vijaykrishnan, Chita R. Das, 2011, on p. 389-399

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni, 2011, on p. 45-52

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, N. Vijaykrishnan, Chita R. Das, 2011, on p. 69-80

Experimental staggered-source and N+ pocket-doped channel III-V tunnel field-effect transistors and their scalabilities

Dheeraj Mohata, Saurabh Mookerjea, Ashish Agrawal, Yuanyuan Li, Theresa Mayer, Vijaykrishnan Narayanan, Amy Liu, Dmitri Loubychev, Joel Fastenau, Suman Datta, 2011, Applied Physics Express

Steep switching tunnel FET

Huichu Liu, Suman Datta, Vijaykrishnan Narayanan, 2013, on p. 145-150

Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

D. K. Mohata, R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastenau, D. Loubychev, A. K. Liu, T. S. Mayer, V. Narayanan, S. Datta, 2012, on p. 53-54